Thursday, April 7, 2016 - 11:30am
Location:Traffic 21 Classroom 6501 Gates & Hillman Centers
Speaker:YAN GU, Ph.D. Student http://www.cs.cmu.edu/~ygu1/
With the arrival of new emerging technologies for main memory, the cost of reading from memory will be significantly cheaper than the cost of writing to memory. This rises new challenges to algorithm design since many of the classic algorithms use approximately the same number of reads and writes. My thesis will study several aspects of this asymmetry between read and write costs. First, it will present and study several cost models that account for this asymmetry in various settings, including both sequential and parallel models. Then the thesis will introduce new algorithms and techniques that are more efficient on the new models compared to standard approaches. To justify whether the approaches and algorithms translate to better efficiency on real hardware, I will attempt to run experiments on upcoming memory systems (this will depend on when the hardware becomes available).
Thesis Committee: Guy E. Blelloch (Chair) Phillip B. Gibbons Anupam Gupta Jeremy T. Fineman (Georgetown University)
Copy of Thesis Summary